Verification of in-order execution in pipelined processors

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques that allow exploration, evaluation, customization and validation of different processor pipeline configurations, tuned for a specific application domain. We propose a novel FSM-based modeling of pipelined processors and define a set of properties that can be used to verify the correctness of in-order execution in the pipeline. Our approach leverages the system architect’s knowledge about the behavior of the pipelined processor (through our ADL constructs) and thus allows a powerful top-down approach to pipeline verification.